JTAG (Joint Test Action Group) is an international standard test protocol (IEEE 1149.1-compatible), the main chip for internal testing. Now most of the senior JTAG devices are in support of the agreement, such as the DSP, FPGA devices, and so on. JTAG interface is the standard 4-wire: TMS, TCK, TDI, TDO, respectively, for model selection, clock, data input and output data line.
JTAG was first used to test the chip, the basic principle is that the device within the definition of a TAP (Test Access Port test visit I) through a dedicated JTAG test tools to conduct an internal node for testing. JTAG test allows multiple devices through the JTAG interface tandem together to form a JTAG chain, to achieve the various components were tested. Now, JTAG interface is also commonly used in the realization of ISP (In-System rogrammable online programming), FLASH programming and other devices.
JTAG programming through online programming, the traditional production process in the first of the chips are pre-programmed to be loaded to change the board and simplify the process for the first device fixed to the board, and then JTAG programming, thus greatly Speed up the progress of the project. JTAG interface chips within the PSD all parts of the program
JTAG some note
Usually by the JTAG roughly two categories for testing of the electrical characteristics of chips, chip testing whether there is a problem for a class Debug; JTAG general support within the CPU include the two modules.
A JTAG Debug interface module containing the CPU, the clock as long as normal, you can access through the JTAG interface CPU's internal register and linked to the CPU bus equipment, such as FLASH, RAM, SOC (such as the 4510 B, 44Box, AT91M series) - Module register, as UART, Timers, GPIO, and so on the register.
Above that the only JTAG interface has the ability to use these features, the software also need to meet the specific realization of the specific features from the software decision.
For example, download RAM to function. SOC understand the know, to use an external RAM, SOC DataSheet reference to the need to register that set up the base address RAM, bus width, access speed, and so on. Some SOC will also need to Remap, in order to work correctly. Firmware run, these settings Firmware from the initial process is complete.However, if the use of JTAG interface, the relevant register may be still in power values, even when the wrong values, RAM does not work, so downloading is bound to fail. To normal use, must be to find ways to set up RAM. In ADW, in the Console window can be ordered through the Let set in AXD in the Console window can be ordered through the Set set.
Below is a set AT91M40800 the command sequence, closing interruption, set CS0-CS3, and Remap, applicable to AXD (ADS with the Debug)
setmem 0xfffff124,0xFFFFFFFF,32 --- close all interrupted
setmem 0xffe00000,0x0100253d,32 --- set CS0
setmem 0xffe00004,0x02002021,32 --- set CS1
setmem 0xffe00008,0x0300253d,32 --- set CS2
setmem 0xffe0000C,0x0400253d,32 --- set CS3
setmem 0xffe00020,1,32 --- Remap
If the ADW (SDT with the DEBUG) in use, would read as follows:
let 0xfffff124=0xFFFFFFFF --- close all interrupted
let 0xffe00000=0x0100253d --- set CS0
let 0xffe00004=0x02002021 --- set CS1
let 0xffe00008=0x0300253d --- set CS2
let 0xffe0000C=0x0400253d --- set CS3
let 0xffe00020=1 --- Remap
To facilitate the use, the order can be saved as a file config.ini, in the Console window to enter ob config.ini implementation.
The use of other debug, roughly similar, but orders and orders in different formats.
RAM settings, set up the register and register and the value must be set up to run the program in line.The general objective of compiling documents are generated ELF format, or a similar format, including a targeted operation code address, address of the running time to determine Link. Debug download files in accordance with the ELF in the address information to download the address specified. If the RAM in the base address is set to 0 x10000000, compiled in the time specified address in the beginning of Firmware 0 x02000000, the download time, the target code will be downloaded to 0 x02000000, apparently downloaded will fail.
Through JTAG download all should be closed before the interruption, which closed at initialization and Firmware disruption of the same reasons. JTAG interface in the use of the time, the interruption can be unknown, especially FLASH executable code, there are circumstances, there may be some that can be interrupted. End the use of JTAG download code, to be implemented, it may have on the completion of the initial disruption, leading to abnormal procedures. Therefore, the need to close interruption, the general disruption by setting the SOC control register completed.
The use of JTAG write Flash. In theory, through the JTAG bus on the CPU can access all the equipment, so should be able to write FLASH, but FLASH RAM into the ways and very different from those in need of special orders, and different FLASH erase, programming different order, And block the size, number of different, it is difficult to provide this function. Therefore, the general Debug does not provide written Flash function, or only a small amount of support of several Flash.
At present I know, for ARM, this software provides only FlashPGM write FLASH functions, but also the use of trouble. AXD，ADW都不提供写FLASH功能。 AXD, ADW not provide written FLASH functions. Flash the way I wrote when he wrote a simple procedure, devoted to write the target board FLASH, using JTAG interface, downloaded to the target board, then to the goal of programming code with a BIN format, but also to target under Board (address and the process of burning FLASH address different), then run the burning FLASH have downloaded the program.This approach is used, rather than the written FlashPGM Flash, speed seems to be faster.
On the simple JTAG cable.
At present, there are all sorts simple JTAG cable, in fact, only a level conversion circuit, also play a protective effect. JTAG logic running on a PC by the software, so in theory, any simple JTAG cables, can support a variety of applications software, such as Debug, and so on. I had to use the same JTAG cable write Xilinx CPLD, AXD / ADW debugger. Key to the support of the software, most software settings are not functional and thus can only support a JTAG cable.
On the simple JTAG cable speed.
JTAG is a serial interface, I use a simple print JTAG cable, I use the print output with the characteristics of latches, the use of software through the I / O have a JTAG timing. JTAG standard by the decision, through JTAG write / read a series of bytes to the operation, according to my analysis, using a simple JTAG cable, I use print, through a JTAG output bytes to the target board, an average of 43 LPT I / O, in my machine (P4 1.7G), per second can be carried out about 660 K, I / O operations, so download speeds about 660 K/43, equivalent to about 15 K Byte / S. For other machines, I / O speed of roughly The same, usually in the 600 K ~ 800K.
On how to improve the JTAG download speed.
Obviously, using a simple JTAG cable can not increase speed. To improve the speed, there are generally two approaches,
1. The use of embedded systems to provide JTAG interface between the computer and embedded systems through USB / Ethernet connected, which requires the use of MCU.
2. The use of CPLD / FPGA to provide JTAG interface, CPLD / FPGA and computer interface between the use of EPP (General Computer LPT support EPP mode), EPP interface computer and CPLD / FPGA data transfer between, CPLD / FPGA completed JTAG timing.
